This invention relates to a wireless transmitter/receiver having a function of adjusting, by way of closed-loop feedback control, the timing of a transmission signal. In particular, the invention relates to a wireless transmitter/receiver that employs EER to adjust the timing of sending an r (amplitude) component and a θ (phase) component.
For transmitters installed in base stations and terminals of cellular phone and other wireless communication systems, methods have been developed to separate a transmission signal into two components, process the two separately, and then recombine them as a transmission output. Known examples of such methods include one in which a transmission signal is separated into an I signal and a Q signal to be processed separately, and EER (Envelope Elimination and Restoration) in which a transmission signal is separated into an r (amplitude) component and a θ (phase) component to be processed separately.
However, signals created by separating one signal into two components to be processed separately differ from each other in signal propagation delay time in the case where processing circuits of the two components are arranged to present different signal path lengths. The separated signals could also differ from each other in signal processing time if different processing circuits are used to process the two. These result in disordered timing of recombining the separated signals into one signal and lowered quality of the recombined signal.
In EER, an r signal and a θ signal are combined, after receiving supply voltage modulation and frequency conversion, respectively, into one signal by a saturated power amplifier, which has high efficiency (see Je-Kuan Jau, “Linear Interpolation Scheme for Compensation of Path-Delay Difference in an Envelope Elimination and Restoration Transmitter”, pp 1072-1075, Proceedings of APMC2001). The power consumption of a power amplifier which amplifies a transmission signal in a communication device constitutes a very large portion of the total power consumption of the communication device, and improving the power amplifier efficiency is a technical objective to be reached. EER addresses this objective by using a saturated power amplifier, which is high in efficiency, and is considered to be effective in reducing the size, cost and power consumption of a communication device.
A problem of EER is that it is liable to give r and θ signals different delay amounts from each other. While a supply voltage modulation circuit to process the r component is composed of, for example, a DC-DC converter, a frequency converter to process the θ signal is composed of a mixer or the like. Because of the vastly different circuit elements used by the two circuits, the delays caused in the process of signal processing mess up the timing of recombining the signals into one signal and greatly lower the quality of the recombined signal.
FIG. 7 is a waveform chart showing the principle of degradation in transmission signal quality due to delays of r and θ signals in EER.
When a sine wave is inputted to a transmitter that employs EER, the waveform of an amplitude component r (θ) 101 is that of a sine wave folded back along the x axis whereas a phase component p (θ) 102 forms a square wave. Normally, the folding back of the r (θ) 101 synchronizes with the phase inversion of the p (θ) 102. Here, consider the case where the phase inversion of the p (θ) 102 is behind the folding back of the r (θ) 101 by τ. A signal S (θ) 103, which is obtained by recombining these r (θ) 101 and p (θ) 102, experiences discontinuous phase inversions for the period τ, causing sharp peaks in an error signal u (θ) 104. This error signal component turns into spurious output (noise) and lowers the quality of the signal. In order to obtain a desired signal quality, the delay difference between the r signal and the θ signal somehow has to be adjusted to align the folding back and the phase inversion with each other.
FIG. 8 is a block diagram illustrating a conventional timing adjustment method for a wireless transmitter/receiver that employs EER. In FIG. 8, the amount of delay along a signal path for r (amplitude) 201 and the amount of delay along a signal path for θ (phase) 202 are made equal to each other by inserting a delay Δdd, which corresponds to the delay difference, Δdr minus Δdθ, to one of the paths where a delay caused by a circuit element is smaller (here, Δdr is larger than Δdθ and the delay Δdd is given to the θ side). It is a digital region where Δdd is inserted in FIG. 8 and, when Δdd is an integer multiple of the clock cycle, the adjustment can be made by simply delaying the θ signal by n clocks with the use of a shift register 203 or the like.
Usually, the delay scale is smaller than one clock and external factors such as a temperature variation make delay fluctuate with time. Je-Kuan Jau proposes a method of adjusting delay at a precision of ½ clock with the use of a digital filter, which performs a linear interpolation on a transmission signal. This structure uses, as FIG. 8 shows, a single master clock source 206 (fixed frequency) to drive digital-to-analog converters (DAC) 204 and 205 of the two paths.
Described next is an example of a timing adjustment method using a feedback (Fb) circuit for a wireless transmitter/receiver that employs other systems than EER.
FIG. 9 is a block diagram showing a timing adjustment method for a transmission signal and a feedback signal in a predistortion (distortion compensation) transmitter (see JP 2001-189685 A).
In FIG. 9, a feedback circuit 301 receives a signal that has been amplified by a power amplifier (PA) 302 and compares the amplified signal against the original transmission signal to measure the amount of nonlinear distortion caused along a transmission signal path (signal path for Tx) 303 including the power amplifier 302 and other elements. A pre-distortor co-efficient calculation unit 304 calculates a coefficient that gives a distortion of the reverse characteristic to cancel the non-linear distortion, and sets the obtained coefficient to a pre-distortor 305. The pre-distortor 305 applies a non-linear distortion determined by the set coefficient to the transmission signal, which is then sent to a frequency-conversion and amplifier unit 307 through a DAC 306.
Meanwhile, in order to align the transmission signal and the feedback signal with each other for comparison, a delay time calculation unit 308 detects the delay difference between the two and determines the amount of delay of a shift register 309 (Δd1) and the amount of delay of a variable delay element 310 (Δd2). The delay amount Δd1 of the shift register 309 corresponds to a delay for the transmission signal by an integer multiple of the clock cycle. The delay amount Δd2 of the variable delay element 310 corresponds to a delay on the 1/n clock-basis of the clock phase of an analog/digital converter (ADC) 311, which converts the feedback signal into a digital signal. In this structure, the same single master clock source is used to drive the DAC 306 and the ADC 311, and the clock phase of the master clock source is fixed.